1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having an epitaxial layer and the method of forming the epitaxial layer.
2. Description of the Prior Art
With the trend of miniaturization of semiconductor device dimensions, the scale of the gate, source and drain of a transistor has dropped in accordance with the reduction of the critical dimension (CD). Due to the physical limitation of the materials used, the decrease of the gate, source and drain scale results in the diminution of the number of carriers that determine the magnitude of the current in the transistor element, which can adversely affect the performance of the transistor. Accordingly, in order to boost up a metal-oxide-semiconductor (MOS) transistor, increasing carrier mobility is an important consideration in the field of current semiconductor technique.
In the conventional technologies, a selective epitaxial growth (SEG) process is used to form a strained silicon layer. For example, after the formation of the gate, a silicon-germanium (SiGe) layer is formed in the predetermined location of the source/drain region, in which the lattice constant of silicon (Si) is 5.431 angstroms (A), and the lattice constant of germanium (Ge) is 5.646 A. The lattice constant of the SiGe layer is larger than the lattice constant of Si, which modifies the band structure of Si, and leads to the formation of a compressive strained silicon layer. The strained silicon layer induces stress in the channel region of PMOS transistor and enhances carrier mobility.
In order to meet the various requirements of consumers, electronic products are commonly constituted of various kinds of element regions, having different functions. In accordance with the demands of specifications and characteristics, each element region has a specific pattern density. To avoid a process deviation caused by the micro-loading effect, the semiconductor processes, such as the selective epitaxial growth process, may be respectively performed on the corresponding regions according to the pattern density. However, this approach affects the manufacturing costs and extends the manufacturing time. Therefore, establishing a semiconductor process simultaneously applicable to all of the element regions having individual pattern densities, without micro-loading effect, is an important issue in this field.